The present invention relates to a semiconductor integrated circuit and manufacturing method thereof and, in particular, relates to a power integrated circuit having construction which enables execution of wire bonding immediately above an active circuit region by utilizing a POE (Pad on Element) technique, namely, a technique for disposing a pad immediately above a semiconductor device, and to manufacturing method thereof.
In recent years, together with widespread use of information technology, needs for speeding up and low power consumption feature have been increasing to be developed as capabilities of electronic equipment such as computers, information storage devices, cellular phones, and portable cameras.
As factors having significant influences on performance of these electronic equipment, core semiconductor electronic parts such as power supply, motor driver, and audio amplifier are mentioned, and as an item which has significant influences on performance of these semiconductor parts, power integrated circuit incorporating power device is mentioned. Therefore, for performance of semiconductor elements constituting the power integrated circuit, requests for further speeding up and lower power consumption feature have been becoming remarkable.
In the meantime, as general requests from the ordinary market, in addition to above-mentioned speeding up and low power consumption feature, major improvements of power devices and circuit characteristics are desired. There are many requests for low-cost and reliable construction and method which are enabled by formation of bond of wire balls and solder balls on immediately above the active circuit region, and many proposals are presented.
Hereafter, first, conventional technology used before introduction of POE technology, a technology by which a pad is provided immediately above the semiconductor device, will be explained briefly.
A member connecting a pad and an external lead frame is a bonding wire. As materials used for the bonding wire, pure or alloy gold, copper, and aluminum are mentioned. When gold is used as the material, diameter of the bonding wire normally used is in a range from approximately 20 to 50 μm, and for wire ball bonding, a ball is normally mounted to a chip. Accordingly, when a ball is crushed to typical nail-head profile by a bonding capillary at bonding work, the area of the pad should be large enough to enable securement of the ball. Since diameter of the ball in free state is typically in a range from approximately 1.2 to 1.6 times the wire diameter, profile of a contact pad should be a square in a range from approximately 50×50 μm-150×150 μm depending on process parameters. Further, when solder ball is used for connecting member, ball diameter is typically in a range from approximately 0.2 to 0.5 mm, while the area of the contact pad should be a square in a range from approximately 0.3 to 0.7 mm. Here, expression of “solder ball” does not necessarily mean that solder contact is spherical, and diversified profiles including semispherical, half dome, cut conical shape or ordinary bump may be used. Accurate shape is depending on deposition technology, reflow technology, and material composition.
Further, contact pads are normally disposed in essentially straight array along with circumference of the chip, thereby consuming large area “silicon resources” (chips are produced on a substrate made predominantly of silicon semiconductor materials). Semiconductor circuits emerged recently require large numbers of contact pads and its number could reach frequently several hundreds even with ground connection and power connection alone. If signal connection is included, contact pads over 1000 pieces are necessary, thereby sacrificing a large amount of precious silicon resources.
Further, it is known from experiences over several years that wire bonding process exerts a sizable stress to a layer under the metal and dielectric body. Causes for this problem are impact of bonding capillary (nail-headed contact is formed by crushing a golden ball), frequency and energy of supersonic vibration of bonding capillary and golden balls (oxidized aluminum film on the surface of the exposed metal layer is broken), and time and temperature of the process (to initiate formation of inter-metal compound of gold/aluminum deposition). In order to avoid risks for generation of cracking or crater to a layer under the bonding pad due to stress during wire bonding process or stress given by device actuation after multiprobe test and assembly, design rules relating to layout of semiconductor integrated circuits, which prohibit circuit structure disposed in the region under the bonding pad and avoid the use of dielectric body materials which are damaged easily and are mechanically weak, are established in the past several years. For this reason, a large quantity of silicon resources is necessary to provide bonding pad alone.
Against such a background, requests for speeding up and low power consumption feature of semiconductor integrated circuits as mentioned above are increasing together with substantial improvement of power device and circuit characteristics, and request for low-cost and reliable construction and method which are enabled by formation of bond of wire balls and solder balls immediately above the active circuit region.
[Speeding Up of Semiconductor Integrated Circuits]
First, factors which disturb speeding up of semiconductor integrated circuits are delay in MOS transistor itself and wiring delay by wirings located at an upper layer thereon. With conventional technology, delay in MOS transistor itself was reduced by fine technology which could make gate length shorter. However, as delay in MOS transistor itself is made smaller, problems associated with wiring delay are becoming outstanding accordingly.
Then, for a purpose of reducing the wiring delay, it is attempted to employ an insulation film (low-dielectric constant film) with low dielectric constant to the insulation film sandwiched between wirings. Meanwhile, with a low-dielectric constant film which realizes dielectric constant not more than 3.0, mechanical strength is greatly reduced compared to a silicon oxidized film which is used conventionally, and problems arise in assembly step responsible for packaging of semiconductor integrated circuits, especially in wire bonding step, upon completion of diffusion step responsible for circuit formation of semiconductor integrated circuits.
Specifically, since mechanical strength of an interlayer insulation film is not sufficient, if wire bonding is performed on the pad mounted on the semiconductor integrated circuit, impact load of the wire bonding is conveyed to the interlayer insulation film immediately below the pad via the pad, thereby greatly deforming the interlayer insulation film. As a result, a crack is caused to the interlayer insulation film which results in poor reliability due to separation of the pad or separation of the interlayer insulation film. Further in recent years, for the sake of reduction in costs by reducing dimensions of the semiconductor elements, a semiconductor element with a pad mounted on transistors constituting an active circuit region is developed. With this semiconductor, if a low-dielectric constant film with low mechanical strength is used between wirings or for the interlayer insulation film, the transistor is damaged due to that the low-dielectric constant film is deformed by impact of wire bonding and the impact can be easily conveyed to the transistor, thereby causing poor quality.
In the meantime, according to Patent Document 1 (Japanese Patent No. 2974022), a metal layer is formed immediately below the pad so as to sandwich an interlayer insulation film, the metal layer and the pad are connected by a via, an impact exerted to the interlayer insulation film by wire bonding is then received by the metal layer and at the same time, possible deformation of the metal layer in impact exertion direction is supported by the via. As mentioned, according to Patent Document 1, damage to the transistor by wire bonding is suppressed by providing a pad structure which makes up reduction in mechanical strength of the interlayer insulation film formed immediately below the pad.
Meanwhile, when copper is adopted as the metal material, copper wiring will be formed by damascene process. If the area of the copper pattern, which is soft in nature, is made greatly large, its center portion is scraped by CMP (Chemical Mechanical Polishing) performed for flattening of plated copper after electroplating of the copper, and its film thickness is made very thin; this is referred to as dishing. Further, in order to form a fine via pattern in the lower layer, if the area of copper pattern is made greatly large by thinning of film thickness of the metal layer, the copper is scraped thoroughly by CMP at certain portion.
In this regard, with the technology disclosed by Patent Document 1, at formation of a second metal layer, namely at copper formation, above-mentioned phenomenon occurs. When center portion of the copper pattern is made thinner or copper is scraped thoroughly as mentioned above, impact of wire bonding received by the interlayer insulation film is increased and possibility of crack generation increases.
In contrast, according to Patent Document 2 (Japanese Patent No. 3725527), a pad structure, which is capable of preventing damage due to wire bonding with regard to an insulation film immediately below the pad and transistor, is provided. Namely, a semiconductor apparatus of the Patent Document 2 comprises a first electrode comprising a conductive layer, an outside connection electrode comprising a conductive layer formed on the first electrode, a second electrode of at least one layer connected via the first electrode and a through-hole to lower part of the first electrode, and has many convex configurations at periphery of the second electrode.
In this way, with such a construction that a metal layer sandwiched by an uppermost layer metal and the interlayer insulation film (hereafter referred to as the lower layer metal) is connected by the via, it is possible to prevent deformation or crack of the low-dielectric constant film adopted between wirings immediately below the pad and to the insulation film between layers due to impact of wire bonding. In other words, since the uppermost layer metal is supported by the lower layer metal against impact of wire bonding, no deformation occurs even if exposed to impact of wire bonding. As a result, impact of wire bonding conveyed to the low-dielectric constant film that serves as the interlayer insulation film immediately below the pad is suppressed, thereby preventing deformation or crack occurrence of the low-dielectric constant film.
Further, for the sake of prevention of dishing of CMP due to the enlarged area of the lower layer metal, many convex configurations are provided at periphery of the lower layer metal, the surface area of the lower layer metal is then enlarged, adhesion with the interlayer film is enhanced, and hence damage to the transistors due to impact of wire bonding can be reduced and at the same time, crack occurrence to the interlayer insulation film can be prevented.
As mentioned above, according to the pad structure employed in Patent Document 2, damage of the insulation film immediately below the pad and transistors due to wire bonding is prevented and this eventually contributes to speeding up of semiconductor integrated circuits.
[Lower Power Consumption Feature of Semiconductor Integrated Circuits]
Next, what impairs lower power consumption attempt of semiconductor integrated circuits is realization of a power integrated circuit incorporating a power device while the chip area is made as small as possible utilizing miniaturization MOS process and effectively utilizing the chip area of semiconductor products. For such power integrated circuit, for the sake of realization of lower power consumption feature, PWM (Pulse Width Modulation) driving technology is normally used for driving of the power device. With the PWM driving, reduction in ON resistance of the power device is an important process technology which results in lower power consumption feature.
Patent Document 3 (US 20020011674A1) proposes conventional related art by which ON resistance of the power device is reduced as much as possible utilizing POE technology. Namely, in a power integrated circuit which enables wire bonding immediately above an active circuit region portion, a plurality of contact pads are disposed immediately above the bus leading to electrodes of the power transistor utilizing POE technology, and a plurality of contact pads and lead frames are connected by bonding wire. With these features, resistance value and current pathway from the connecting member to the electrode are minimized, and electric characteristics of the power transistor can then be improved.
FIG. 13 shows simplified plan view of a part of the semiconductor integrated circuit described in Patent Document 3 and electric diagram.
As shown in the plan view of FIG. 13, an active region 2 of the power transistor is formed in an IC chip 1, and on the active region 2 are formed a first bus 3 which is composed of sheet-like metal and is connected to all source electrodes, and a second bus 4 which is connected to all drain electrodes. On the first bus 3 and the second bus 4 are provided each three contact pads 5 and are connected commonly to each of the busses. Three contact pads 5 on the first bus 3 are disposed so as to be bilaterally-symmetric with three contact pads 5 on the second bus 3. A bonding wire 6 connecting each of the contact pads 5 and an external lead frame 7 is provided.
The electric diagram shown in FIG. 13 schematically shows electrical features relating to operations of the power transistor brought by that a connecting member to the lead frame 7 is disposed on the power transistor. Resistance Rs across source and drain of transistor itself, spreading resistance (bus resistance) Rn10, Rn20, Rn30 on the bus and various wire resistances Rb10, Rb20, Rb30 are shown on the electric diagram.
As shown in FIG. 13, the electric circuit looking from the lead frame 7 is such a resistance circuit where bus resistances Rn10, Rn20, Rn30 are connected in series to each of wire resistances Rb10, Rb20, Rb30 of three bonding wires 6 which are connected in parallel to the lead frame 7, and across source-drain resistance Rs of the transistor itself is further connected. In this way, by the fact that each of bus resistances Rn (10-30) is connected in series to various wire resistances Rb (10-30), bus resistance Rn (10-30) and wire resistance Rb (10-30) are eventually connected to each other in parallel, and whole resistance composed of source-drain resistance Rs, bus resistance Rn (10-30) and wire resistance Rb (10-30) is reduced. In other words, since voltage drop related to across source-drain resistance Rs, bus resistance Rn (10-30) and wire resistance Rb (10-30), and corresponding device effects are lowered, transistor characteristics are improved.
Meanwhile, as shown in Patent Document 3, for the purpose of minimization of resistance value and current pathway from the connecting member to the electrode, in the power integrated circuit capable of performing wire bonding immediately above the active circuit region portion, on each one of busses to be connected to the source electrode and busses to be connected to the drain electrode of the power transistor are disposed a plurality of contact pads in distributed fashion so as to be located immediately above the power transistor.
However, busses connected to the source electrode and the drain electrode of the power transistor are all commonly connected to a plurality of contact pads, it is difficult to attempt minimization of IC chips by mask layout of the semiconductor integrated circuit (IC chip) incorporating the power transistor and at the same time to equalize currents flowing through each of power transistors by identifying current routes leading to each of power transistors.
Further, there was such a problem that when a large current is introduced to the power transistor, since busses connected to the source electrode and the drain electrode of the power transistor are all commonly connected to each of a plurality of contact pads, current crowding is caused to the power transistor thereby giving a damage thereto depending on types of the power device (e.g., power NPN transistor) and on layout of the bus connected to the electrodes, and reliability of the semiconductor integrated circuit is eventually hampered.